IBIS Macromodel Task Group Meeting date: 17 July 2012 Members (asterisk for those attending): Agilent: Fangyi Rao * Radek Biernacki Altera: * David Banas Julia Liu * Hazlina Ramly Andrew Joy Consulting: Andy Joy Ansys: Samuel Mertens * Dan Dvorscak * Curtis Clark * Steve Pytel Arrow Electronics: Ian Dodd Cadence Design Systems: Terry Jernberg * Ambrish Varma Feras Al-Hawari Cavium Networks: * Johann Nittmann Celsionix: Kellee Crisafulli Cisco Systems: Ashwin Vasudevan Syed Huq Ericsson: Anders Ekholm IBM: Greg Edlund Intel: * Michael Mirmak LSI Logic: Wenyi Jin Maxim Integrated Products: * Mahbubul Bari Mentor Graphics: * John Angulo Zhen Mu * Arpad Muranyi Vladimir Dmitriev-Zdorov Micron Technology: Randy Wolff * Justin Butterfield NetLogic Microsystems: Ryan Couts Nokia-Siemens Networks: * Eckhard Lenski QLogic Corp. * James Zhou Sigrity: * Brad Brim Kumar Keshavan Ken Willis SiSoft: * Walter Katz Todd Westerhoff Doug Burns * Mike LaBonte Snowbush IP: Marcus Van Ierssel ST Micro: Syed Sadeghi Teraspeed Consulting Group: * Scott McMorrow * Bob Ross TI: Casey Morrison Alfred Chong Vitesse Semiconductor: Eric Sweetman Xilinx: Mustansir Fanaswalla * Ray Anderson NOTE: An unidentified caller joined about 44 minutes into the meeting. The meeting was led by Arpad Muranyi ------------------------------------------------------------------------ Opens: - Michael M: I may be called away briefly -------------------------- Call for patent disclosure: - None ------------- Review of ARs: - Bob to propose a simpler way for addressing the needs of parameter passing under [External Model] and [External Circuit] - not done ------------- New Discussion: Arpad introduced the topic of package modeling improvements: - Arpad: The need goes beyond electrical modeling changes. - We may need to review the fundamental syntax for package models. - We need to hear from model makers on this. Michael M showed a presentation "Package Model Format Needs": - Slide 2: - Michael M: The models described here are for customer use. - Users create the connection between the package and the buffers/system themselves. - Scripts may be provided to assist with this. - Slide 4: - For SerDes we usually do not provide structural data. - Current work typically models 3 diff pairs. - These are often pair coupled, sometimes all 6 coupled together. - W-line lengths are passed in from outside using params. - Sometimes a 9 corner structure is needed if model portions don't change the same way. - The models are oriented toward time domain analysis. - Walter: This assumes no crosstalk between TX and RX? - Michael M: There is a strong tendency to not use interleaving. - Walter: That is not the case for all IC vendors. - All SPICE elements can be represented in IBIS-ISS? - Michael M: Yes, but that is not tested. - Walter: An s12p could be created and used in frequency domain because it is LTI. - Michael M was called away - Scott: The 3 diff pair limitation is arbitrarily small. - It should support an arbitrary count. - Arpad: Agree. - Walter: We have seen 4 aggressors in the package itself. - The pin field underneath may be different. - Scott: At 25G-30G nearly everything in the package is significantly coupled. - It can be around -40dB. - Arpad: What is the significance of the question about FEXT? - Walter: With NEXT the victim is on the same chip as the aggressor. - Aggressor and victim tap coefficients are the same. - The near end crosstalk can be disastrous. - Michael M: About the s12p question we try to avoid s-parameters. - It works somewhat poorly in time domain. - Johann: The w-element is good for frequency domain. - The difficulty is converting back to time domain? - Michael M: Yes, although this does not apply to all use in the time domain. - Johann: Lengths must be given for the w-elements. - This gives away structural information. - Michael M: We are not providing detailed geometry, only some lengths. - There is no layout information. - Slide 5: - Michael M: For memory parts the main difference is that a 10 line structure is recommended. - Arpad: Is the netlist the same across corners? - Michael M: The topology is the same but the cross section can change. - Usually circuit names change. - Users might not be able to implement corners using parameters. - Walter: Passing the name of a w-line might help. - For DDR3 the DQS signal sometimes comes from the TX, sometimes from the RX. - This might violate NEXT/FEXT assumptions. - Michael M: There is no TX/RX line on this slide. - Direction should not be a package model problem. - Steve: It should allow for power and ground rails. - Walter: Can the power/ground sections be independent of signals? - Scott: It depends. - In a wirebond package they are coupled together strongly. - In a stripline with signals between P&G planes there is coupling. - Steve: DDR4 will be even more difficult. - Walter: Should simulators use something like MCP to stitch pieces together? - An IBIS limitation is the resource of peoples' time. - Coupling power and signal in the package increases the problem for IBIS exponentially. - Slide 6: - Michael M: A generic format should not require physical information. - It should be "drop in" for users but "free form" for model makers. - It must be more compelling than a SPICE subcircuit. - Arpad: Is this different from the BIRD 125 proposal? - Michael M: Based on the "don't make me think" principle, yes. Mahbubul: Is there a specific proposal associated with this? - Arpad: No. - Walter: It mostly identifies the structures most commonly used. Arpad: We need to think about what to do next. - Please send any feedback on BIRD 125. - Walter: We should think about using BIRD 125 for Michael's circuits. ------------- Next meeting: 17 Jul 2012 12:00pm PT Next agenda: 1) Task list item discussions ------------- IBIS Interconnect SPICE Wish List: 1) Simulator directives